How to pick an I2C pull-up resistor value

The bus works on the bench with one sensor. Add a second board, a longer cable or a 3.3 V part next to a 1.8 V one, and reads start failing, or the rising edges look like shark fins on the scope. Most of the time the cause is a pull-up value nobody calculated. Someone copied 4.7 kΩ from a breakout board and moved on.

The calculation is short. It gives you a window: a smallest value and a largest value. Any resistor inside the window works. This note walks through both ends with real numbers, then covers what moves the window and how to confirm the result.

Why I2C needs pull-ups at all

I2C lines are open-drain. Every device can pull SDA or SCL low, and none of them can drive it high. The resistor does the pulling up, so the rising edge is an RC charge curve. The falling edge is a transistor and is fast.

That gives two opposing limits:

• A large resistor charges the bus capacitance slowly. The rising edge misses the timing the bus speed allows.
• A small resistor makes the device that is pulling low fight a lot of current. The low level rises above what receivers accept as a valid low.

The window sits between those two. Everything else in this note is how to find its edges.

The smallest value: what a device can sink

When a device pulls the line low, the resistor and the device’s output transistor form a divider. The resistor must be large enough that the device can hold the line below its maximum output-low voltage while sinking the resulting current.

Microchip’s application documentation gives the form: Rp(min) = (VDD − VOL(max)) / IOL, where IOL is the sink current the I2C specification requires of the outputs. Microchip’s pull-up selection page states 3 mA for Standard-mode and Fast-mode. Check the I2C specification and each device’s own datasheet, because some parts specify different low-level behavior, particularly at low supply voltages.

Worked example with a 3.3 V supply, a VOL(max) of 0.4 V and 3 mA:

Rp(min) = (3.3 − 0.4) / 0.003 ≈ 967 Ω

At 5 V the same arithmetic gives about 1.5 kΩ. At a lower supply the minimum falls, which is why 1.8 V buses can use smaller resistors. If any device on the bus is specified for a lower sink current than 3 mA, use its number. The weakest output sets the floor.

The largest value: what the capacitance allows

The rising edge is measured between 30% and 70% of VDD. For an RC charge that takes 0.8473 time constants. So the maximum resistor is:

Rp(max) = t_rise / (0.8473 × Cb)

Here t_rise is the maximum rise time for your bus mode and Cb is the total bus capacitance. Microchip’s page gives the same equation, defines the rise time as running from 0.3 × VDD to 0.7 × VDD, and recommends measuring Cb where you can. Look up the rise-time limit and the maximum bus capacitance for your bus mode in the I2C specification and in the datasheets of the devices on the bus, and use the tightest numbers you find.

Worked examples, all from that one formula:

Mode and load	Rise time limit	Cb	Rp(max)
Fast-mode, light bus	300 ns	100 pF	about 3.5 kΩ
Fast-mode, loaded bus	300 ns	200 pF	about 1.8 kΩ
Standard-mode	1000 ns	100 pF	about 11.8 kΩ

Notice that doubling the capacitance halves the allowed resistor. A bus that was fine at 100 pF has no room left at 200 pF if you picked a value near the top of the window.

Putting the window together

For Fast-mode at 3.3 V with about 100 pF on the bus, the window is roughly 970 Ω to 3.5 kΩ. A 2.2 kΩ resistor sits comfortably inside it. Check the choice both ways:

• Rise time: 0.8473 × 2.2 kΩ × 100 pF ≈ 186 ns, under the 300 ns limit with margin.
• Sink current: 2.9 V / 2.2 kΩ ≈ 1.3 mA, well under what the outputs must handle.

Pick a standard value near the geometric middle of the window rather than at either end. Resistor tolerance and capacitance spread then cannot push you out. If the window is empty, with Rp(min) above Rp(max), the bus is overloaded and you need a slower mode, less capacitance, or a buffer.

What moves the numbers

Capacitance is the unknown. Start from the datasheet pin capacitance of each device. Add the trace, the connector and any cable. Cable capacitance adds up fast, and it is the usual reason a bus that worked on the desk fails in an enclosure. Microchip’s page notes you can exceed the allowed capacitance but only at a lower clock frequency, which is often the cheapest fix. Measure rather than trust the estimate whenever the bus is near its limit.

Pull-ups multiply. Every board with its own pull-ups puts them in parallel, and parallel resistors give a lower value than any one of them. Three modules with 10 kΩ each are about 3.3 kΩ together, and four are 2.5 kΩ. Both are still inside the Fast-mode window above, so a few stacked pull-ups do not break the rise time. The effect pushes you toward the minimum side: the more pull-ups in parallel, the more current every device must sink, and the higher the low level (VOL) climbs. Keep adding modules and you eventually fall below the minimum, which is about 970 Ω in the example. Before adding a pull-up to a schematic, find out what is already on the bus, and recompute the combined value and the sink current. Check the far end of any cable too. Our note on a bus stuck low after a reset covers the opposite failure, where the lines are held rather than slow.

Supply voltage. The minimum scales with VDD, so a bus shared between voltage domains needs a recalculation on each side. Level translators change this too. Some switch-style translators connect the two sides’ pull-ups together, so the sink current each device sees depends on both resistors. Read the translator’s datasheet rather than sizing each side alone.

Power. While a line is held low, the resistor draws VDD / Rp continuously. For a battery product that sleeps with a line low, a small pull-up is a standing leak. At 2.2 kΩ and 3.3 V that is 1.5 mA for as long as the line stays low. Make sure firmware leaves both lines idle high before sleep, and use the largest value the window allows if sleep current matters.

Series resistors and ESD parts. Any added series resistance raises the voltage the line reaches when pulled low, which shrinks the minimum side of the window. Protection diodes add capacitance, which shrinks the maximum side.

Check it on the board

Calculation gets you to a good first value. A scope tells you if it worked.

1. Probe SDA and SCL at the device farthest from the controller, with a short ground spring, not a long ground lead. A long lead adds its own ringing.
2. Measure the rise from 30% to 70% of VDD and compare it with the limit for your mode.
3. Check the low level during an acknowledge. It should sit comfortably below the receivers’ low threshold.
4. Repeat with the real cable and the enclosure closed, and with every optional module fitted.
5. Run the bus at the temperature extremes you ship to if the capacitance of any part is likely to change.

If the edge is too slow, first remove capacitance or pull-ups that are not needed, then lower the resistor. If the low level is too high, raise the resistor or confirm which device is the weak one.

How we approach it

We size pull-ups from the actual parts, cable and supply domains on the schematic, then confirm the edges on the bench before a board goes to assembly. If you have a bus that misbehaves, send the schematic, the part numbers on the bus, the cable length, and a scope capture of SDA and SCL if you have one.